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NJU26105
3.1ch Outputs Digital Signal Processor
General Description
Package
The NJU26105 is a high performance 24-bit digital signal processor. The NJU26105 provides `eala' 3D Surround function, `eala BASS' Dynamic Bass Boost function, 5band-PEQ, AGC, and Tone Control. These kinds of sound functions are suitable for TV, mini-component, CD radio-cassette, speakers system and other audio products.
NJU26105FR1
FEATURES
*`eala' 3D Surround Function *`eala BASS' Dynamic Bass Boost Function * 5band-PEQ * Automatic Gain Control * Tone Control * 3.1-Channel Outputs including Center speaker and Subwoofer
Digital Signal Processor Specification
* 24bit Fixed-point Digital Signal Processing * Maximum System Clock Frequency : 38MHz * Digital Audio Interface : 2 Input ports / 2 Output ports * Master / Slave Mode * Master Mode MCK : 1/2 fclk, 1/3 fclk ex. MCK = 384Fs(1/2) or MCK = 256Fs(1/3) at fclk=768Fs * Two kinds of micro computer interface * I2C bus (standard-mode/100kbps) * Serial interface (4 lines: clock, enable, input data, output data) * Power Supply : 2.5V ( 3.3V Input tolerant ) * Package : QFP32-R1 The detail hardware specification of the NJU26105 is described in the ` NJU26100 Series Hardware Data Sheet'.
Ver.2005-02-21
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NJU26105
Function Block Diagram
AD1/SDIN AD2/SSb
NJU26105
DSP ARITHMETIC UNIT SERIAL AUDIO INTERFACE BCKO LRO 24-BIT x 24-BIT MULTIPLIER ALU L/R out C/SW out L/R in L/R in SDO0 SDO1 SDI0 SDI1 BCKI LRI
SCL/SCK
SDA/SDOUT
SERIAL HOST INTERFACE
PROGRAM CONTROL
RESETb MCK XI XO TIMING GENERATOR ADDRESS GENERATION UNIT
DATA RAM
FIRMWARE ROM
GPIO AND CONFIGURATION INTERFACE
SEL1
Fig. 1 NJU26105 Block Diagram
DSP Block Diagram
Trim IN SDI0 AGC eala Tone Control 5Band PEQ SDI1 ealaBass 4Band +HPF C Vol SW LPF Vol M/V L/R Vol
OUT
Fig. 2 NJU26105 Function Diagram
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NJU26105
Pin Configuration
VDDR VDDR VDDC VDDC VSSR
24
VSSR
23
VSSC
VSSC
22
21
20
19
18
17
SDI0 SDI1 TEST1 LRI BCKI MCK BCKO LRO
25
WDC VSSC VDDC RESETb VSSO XO XI VDDO
16
26 15 27 14 28
NJU26105
13
29 30 31 32 1
12 11 10 9
2
3
4
5
6
7
8
Fig. 3 NJU26105 Pin Configuration
TEST0
SEL1
SDO0
SCL/SCK
SDA/SDOUT
AD1/SDIN
AD2/SSb
SDO1
Pin Description
Table 1 Pin Description
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol TEST0 SDO1 SDO0 SEL1 SCL/SCK SDA/SDOUT AD1/SDIN AD2/SSb VDDO XI XO VSSO RESETb VDDC VSSC WDC I/O O O O I *2 I I/O I I -I O -I --O *2 Description Open Audio Data Output 1 C/SW Audio Data Output 0 L/R Select I2C or Serial bus I2C Clock / Serial Clock I2C I/O / Serial Output I2C Address / Serial Input I2C Address / Serial Enable OSC Power Supply +2.5V X'tal Clock Input OSC Output OSC GND RESET (active Low) Core Power Supply +2.5V Core GND Clock for Watch Dog Timer No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol VDDC VDDC VSSC VSSC VDDR VDDR VSSR VSSR SDI0 SDI1 TEST1 LRI BCKI MCK BCKO LRO I/O --------I I I I I O O O Description Core Power Supply +2.5V Core Power Supply +2.5V Core GND Core GND I/O Power Supply +2.5V I/O Power Supply +2.5V I/O GND I/O GND Audio Data Input 0 L/R Audio Data Input 1 L/R Connect to GND LR Clock Input Bit Clock Input Master Clock Output Bit Clock Output LR Clock Output
*1 I : Input, O : Output, I/O : Bi-directional *2 SEL1 : Input, WDC : Output
Ver.2005-02-21
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NJU26105
Audio Interface
The NJU26105 audio interface provides industry serial data formats of I2S, MSB-first Left-justified or MSB-first Right-justified. The NJU26105 audio interface provides two data inputs, SDI0 and SDI1, and two data outputs, SDO0 and SDO1, as shown in table 2 and 3. The input serial data is selected by the firmware command.
Table 2
Pin No. 25 26
Serial Audio Input Pin
Symbol SDI0 SDI1 Description Audio Data Input 0 L / R Audio Data Input 1 L / R
Table 3
Pin No. 3 2
Serial Audio Output Pin
Symbol SDO0 SDO1 Description Audio Data Output 0 L / R Audio Data Output 1 C/SW
Host Interface
The NJU26105 can be controlled via Serial Host Interface (SHI) using either of two serial bus formats : I2C bus or 4-Wire serial bus. Data transfers are in 8 bits packets (1 byte) when using either format. The SHI operates only in a SLAVE fashion. A host controller connected to the interface always drives the clock (SCL / SCK) line and initiates data transfers, regardless of the chosen communication protocol. The detail I2C bus and 4-Wire Serial bus information are described in the `NJU26100 Series Hardware Data Sheet'.
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Ver.2005-02-21
NJU26105
I C address
2
AD1 and AD2 pins are used to configure the seven-bit SLAVE address of the serial host interface. These pins offer additional flexibility to SLAVE address. 4 addresses could be chosen by AD1 and AD2-pin. The AD1 and AD2-pin addresses are decided by the connections of AD1 and AD2-pin. The AD1 and AD2 addresses should be the same level as AD1 and AD2-pin connections. Table 4 I2C Bus SLAVE Address bit7 bit6 bit5 bit4 bit3 0 0 1 1 1 *AD1 or AD2 address is 0 when AD1 or AD2-pin is `Low'. *AD1 or AD2 address is 1 when AD1 or AD2-pin is `High'.
bit2 AD2*
bit1 AD1*
bit0 R/W
The detail I2C bus timing of the NJU26105 is described in the ` NJU26100 Series Hardware Data Sheet'.
4-Wire Serial Interface
The serial host interface can be configured for 4-Wire Serial bus communication by setting GPIO0 pin (*SEL1 pin)=`High' during the Reset initialization sequence. SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the same time that a read byte is shifted out of the SDOUT pin. Data transfers are MSB first and are enabled by setting the Slave Select pin Low (SSb = 0). Data is clocked into SDIN on rising transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte (MSB) which is latched on the falling transitions of SSb. SDOUT is Hi-Z in case of SSb = `High'. SDOUT is CMOS output in case of SSb = `Low'. SDOUT needs a pull-up resistor when SDOUT is Hi-Z. The detail 4-Wire Serial bus timing of the NJU26105 is described in the ` NJU26100 Series Hardware Data Sheet'.
Ver.2005-02-21
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NJU26105
Firmware Command Table
Host processor can control the NJU26105 via I2C bus or 4-Wire serial bus interface. The following table summarizes the available user commands.
Table 5 NJU26105 Command
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Command Start Command System State Firmware mode select Fs Select / Input Select Master Volume Master Volume Boost Master Volume Smooth Control Channel Balance Output Channel Trim L/R Output Channel Trim C/SW Command Description A command receivable state Serial Mode, Data Width, MCK, BCK, Master / Slave 3D, PEQ, AGC, Tone Control, SW mode 32, 44.1, 48kHz, SDI0, SDI1 0dB to -96dB, -inf Boost : 0, 6, 12, 18, 24dB Smooth Control : 13, 26, 53, 106ms 0dB to -30dB, -inf, L/R 0dB to -96dB, -inf, L/R 0dB to -96dB, -inf, C/SW
AGC Threshold Level -6dBFS to -40dBFS AGC Noise Compressor -50 dBFS to -96dBFS, -inf Threshold Level AGC Attack Time : 0.1, 0.2, 0.5, 1, 2, 5 [sec] AGC Attack Time / Release Time AGC Release Time : 1, 2, 5, 10, 20, 50 [msec] AGC Boost : 0, 6, 12, 18, 24dB AGC Ratio / Boost AGC Ratio : 20:1, 8:1, 4:1, 2:1, -inf AGC Output Trim 0dB to -31dB AGC BYPASS Trim eala Surround Gain eala Bass Bass fo eala Bass Bass volume eala Bass Treble fo eala Bass Treble gain eala Bass Output Trim eala Bass Attack Time / Release Time Tone Control Bass/Treble Gain EQ band1 mode PEQ1 to 5 / HPF fo PEQ1 to 5 Q PEQ1 to 5 Gain SW fc Version No. Request 0dB to -31dB 0dB to +12dB 40Hz to 315Hz -12dB to +12dB 8kHz, 9kHz, 10kHz, 11kHz 0dB to +6dB 0dB to -31dB AGC Attack Time : 0.1, 0.2, 0.5, 1, 2, 5 [sec] AGC Release Time : 1, 2, 5, 10, 20, 50 [msec] -12dB to +12dB PEQ, HPF 20Hz to 20kHz(20point/decade) 0.33, 0.43, 0.56, 0.75, 1, 1.2, 1.5, 1.8, 2.2, 2.7, 3.3, 3.9, 4.7, 5.6, 6.8, 8.2 -12dB to +12dB 40Hz to 315Hz Firmware Version No. Request
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Ver.2005-02-21
NJU26105
No. 31 32 33 34
Command Status Read AGC Input Level Request AGC Gain Reduction Request No Operation Level
Command Description Status inside DSP is outputted. AGC Input Level is outputted. AGC Gain Reduction Level is outputted. NOP command
License Information
Purchase of I2C components of New Japan Radio Co., Ltd or one of sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard specification as defined by Philips.
Ver.1.01
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
Ver.2005-02-21
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